Investigating NAND functionality in support of intellectual property

Investigating NAND functionality in support of intellectual property

The memory technology space features a range of key players and innovation that is best understood through in-depth technical analysis

Evidence of use is key in any patent action – whether it is part of an investigation, transaction, assertion, defence or prosecution. However, when investigating technology patents, especially in the case of semiconductor or advanced technology products, indications or evidence of use can be harder to find. Publicly available sources of information may illuminate potential areas of use but finding litigation-ready evidence often requires more specific data.

So where do you go when you have exhausted all publicly available documentation to support a technology patent?

Technical analysis includes – and goes far beyond – identifying design wins. It can reveal how something was built, what materials were used, how those materials were processed or combined, how different components within a device are powered and communicate, what voltage inputs and outputs are required to properly operate a device, and so on.

This article examines some of the analytical techniques that can be used to investigate NAND flash devices, and how different types of analysis can help to support different types of patents. What is more, it provides an IP perspective for the NAND patent landscape.

Valuable NAND features

Before undertaking any analysis, it is important to understand what information and features are valuable to the NAND market so that it is possible to make informed IP and product decisions. In terms of NAND, there are several key features:

  • Physical structure – this includes the features, size, materials and number of layers in a memory stack. These details will vary depending on the application. For example, in an automotive application, a single-level cell may be used for reliability, but for increased capacity applications, a multi-level cell may be preferred.
  • Error correction code (ECC) and ECC/retry algorithms – within the NAND there are redundant rows available for yield improvement to overcome defects. It is important to have a good algorithm for detecting these faulty areas, as this will reduce testing time.
  • Pulse verify – in the analogue domain, pulse verify provides the stability to tightly control and adjust threshold levels of NAND operations as they shift over time.
  • Do not disturb function – this ensures that adjacent cells are not disturbed when a cell is being programmed, read or erased.
  • Cache – in the digital domain, cache is now being included within the NAND memory. It may be a separate cache or it may be an area of the memory itself used for this operation. Cache increases the speed of the device by using a faster single-level programming mode and then subsequently rewriting the data in a slower multi-level programming mode as needed or when the device is not busy with requests from the controller.
  • Memory life cycle – as memory ages its performance changes. A good algorithm will adjust to these changes and maintain a reliable performance.

Figure 1 illustrates the basic structure of a solid-state drive (SSD) that includes NAND for memory storage. In this diagram, the middle line denotes the boundary between protocol analysis applied to the digital domain, and waveform analysis performed in the analogue domain.

Figure 1. Boundary between protocol and waveform analysis in a solid-state drive

FIGURE 1. Boundary between protocol and waveform analysis in a solid-state drive

Patent landscape: key players and technology areas

Figure 2 and Table 1 identify the 48 organisations that hold the most patents for technologies in areas aligned to waveform and protocol testing and indicates the ratio of protocol to waveform patents held by each company.

Figure 2. Top organisations with technology patents relevant to waveform and protocol testing of NAND technology

FIGURE 2. Top organisations with technology patents relevant to waveform and protocol testing of NAND technology

Table 1. Categorisation of top US NAND waveform and protocol patent owners

Top six – largest market share

Patent assertion entities (PAE)

Fabless memory

Controller focus

Semiconductor fabricators

  • Samsung
  • Western Digital
  • Micron
  • SK hynix
  • Intel
  • IPValue
  • Conversant
  • Intellectual Ventures
  • Quarterhill*
  • Xperi*
  • Renesas
  • Winbond
  • NXP
  • eMemory
  • Aplus Flash
  • Seagate
  • Phison
  • Marvell
  • Ovonyx Memory
  • Taiwan Semiconductor Manufacturing Company
  • Mubadala
  • UMC

From this, we observe the following:

  • The top six companies by market share hold more than half of the patents considered for this article.
  • Memory solution providers have varied approaches to their portfolios in these technology areas, with some focusing more on protocols and some focusing purely on analogue systems.
  • Patent assertion entities (PAEs), which can buy patents from any source, seem to be more focused on analogue systems.
  • Controller companies are focused on protocols.
  • Fabricators are generally focused on the structure and manufacture of cells (analogue), which the exception of Mubadala, whose portfolio appears to be evenly split between analogue and protocol technologies.

Figure 3 and Table 2 map the patents of the top 48 NAND patent owners to show the key technology areas within a set of patents, and how the various technologies relate to one another. The landscape also indicates the different types of technology or function that can be supported through protocol and waveform analysis.

Figure 3. Landscape of technologies suitable for protocol or waveform analysis

FIGURE 3. Landscape of technologies suitable for protocol or waveform analysis

Table 2. Technologies or functions that can be supported through protocol  and waveform analysis

Protocol – digital

Waveform – analogue

Technology landscape peaks

Features supported by these technologies

Technology landscape peaks

Features supported by these technologies

  • Block
  • Cache
  • Commands
  • Defect
  • ECC
  • Interface
  • Methods
  • Retry
  • Command
  • Mode
  • Algorithm
  • MLC
  • Wear
  • Garbage
  • Boost
  • Cells
  • Device
  • Disturb
  • Element
  • Erase
  • Pulse
  • Reference
  • Region
  • Segment
  • Select
  • Voltage
  • Read
  • Write
  • Erase
  • Pulse
  • Verify
  • Disturb
  • Boost

Protocol analysis investigates implementations in the digital domain to test bulk operations of the analogue functions. This includes:

  • interfaces between chips;
  • commands shared by chips;
  • methods or sequences applied to conduct bulk operations at the block level; and
  • patents that require cache or that involve retry or error correction.

Waveform analysis is used in the analogue domain to test cell structures (material and shape) and electrical operations such as memory cell read, write and erase.

Circuit reverse engineering

Waveform analysis provides information about the signal voltages within a NAND device. However, in order to conduct such analysis, we must know what components of a circuit need testing, where they are and what they do.

As such, circuit reverse engineering is the first step in waveform analysis, as it shows where the nodes of interest are located within the NAND device.

There are roughly 12 steps in the circuit reverse engineering process, from the starting point, a semiconductor chip, to the end result – a completed schematic mapped to various nodes within the chip (see Figure 4).

Figure 4. Interpreted schematic of device connectivity

FIGURE 4. Interpreted schematic of device connectivity

Through this process, the semiconductor die is uncovered and digitally recreated as a set of highly magnified images stitched together. From the images, analysts can identify interfaces, devices and nodes, which can then be tested further.

NAND technology industry roadmap

Determining how much circuit reverse engineering will be needed for a waveform investigation requires an examination of the levels of innovation in the NAND technology industry roadmap.

The companies that represent the majority of NAND revenue are Samsung, KIOXIA (Toshiba), Western Digital, Micron/Intel (IM Flash), SK hynix and Yangtze Memory Technologies Co. Typically, they introduce new generations of NAND solutions every 12 to 15 months.

Each NAND generation includes a significant amount of innovation. Changes have occurred in areas such as:

  • the nodes of the processes used to make the memory;
  • the number of bits per cell;
  • the steady increase in the number of layers in the memory stack; and
  • the periphery circuit under the cell.

Analysis of the physical structures is required to understand the evolution of this technology and how the memories are built. What is more, circuit reverse engineering is undertaken periodically in several of these areas, depending on the impact of the innovation.

There are two key areas of interest on an SSD device to examine:

  • the NAND flash itself – where we gain access to the internal operations of the device (eg, the voltages present on wordlines and bitlines, and other internal signals) – referred to as internal waveform analysis; and
  • the signals passed between the controller and the NAND flash – referred to as protocol analysis.

Internal waveform analysis

Internal waveform analysis provides details of the programming algorithm and measurements of the internally generated voltages required to programme, read and erase memory cells during various device operations and modes. It is done by exposing the signals of interest to traces and actively probing them in order to record the voltages.

This information would generally not be available through any other means.

The key features that are analysed in the analogue domain are delivered by a wide range of patents. For example, completing a read and write function within memories involves many patents across the landscape, as shown in Figure 5. Indeed, a single feature is often delivered by a host of different innovations and refinements.

Figure 5. Range of patents delivering key features in the analogue domain

FIGURE 5. Range of patents delivering key features in the analogue domain

What can be learned?

Based on years of analysis, we can examine how one company’s technology has evolved over time and compare that to the evolution of other manufacturers. Waveform analysis provides:

  • information about signal operations within a device;
  • a comparison of similar devices by different manufacturers (eg, SanDisk/Toshiba’s approach versus Micron’s approach); and
  • a comparison of approaches to successive generations by a single manufacturer, as demonstrated in Figure 6.

Figure 6. Waveform analysis of generations of NAND devices by the same manufacturer

FIGURE 6. Waveform analysis of generations of NAND devices by the same manufacturer

Protocol analysis

Protocol analysis provides details of the command and address structure, as well as high-level details of the SSD controller algorithms. It looks at commands being sent from the SSD to the NAND flash, and the responses coming back from the NAND flash device. This uncovers the timings between individual signals and any unique commands that may be used in reserved command spaces.

The analysis is performed by interposing the memory, capturing the signals with a logic analyser and conducting analysis using custom scripts.

Looking at the patent landscape in Figure 7 as it applies to protocol analysis, we see some of the building blocks that deliver features of the NAND and NAND controller. These are the interfaces between chips, the commands shared and the methods used. Various peaks indicate the resources used for specific functions such as caching for memory speed and error correction.

Figure 7. Range of patents delivering key features in the digital domain

Figure 7. Range of patents delivering key features in the digital domain

The word “command” appears strongly in one area, where a list of commands is used for bulk operations. The word “mode” applies throughout the landscape, as there are modes in the protocol domain and modes of operation in the analogue domain. “Algorithm”, which defines a sequence of steps, is more focused in the protocol area. Areas such as multi-level cell and garbage collection are included in the large peak under methods.

Under review

The NAND IP market is a global industry with a rich variety of innovations and patents. The players identified in the patent study represent many of the major markets; between one-quarter and one-third of the US patents included in the study are pursued in the national phase around the world.

Patented innovations in the NAND space begin at the materials level and journey through fabrication, structure, circuits, power, reliability and through-put. Some of the newest innovations in the market focus around how semiconductors are built and how they increase memory density. As companies continue to develop their product and IP strategies, evidence and data on innovation and patents will become all the more essential.

Action plan

Technical analysis is important to establish evidence of use in any technology, but it can be particularly important in an area as complex as NAND flash devices. Here are a few things to consider when investigating evidence of use:

  • Begin by developing an understanding of the key aspects of the technology, including in areas such as ECC algorithms and memory lifecycle.
  • Build a picture of the patent landscape to determine the strongest rights holders.
  • Each generation of NAND includes a significant amount of innovation, making structural analysis even more important for those looking to understand the space.
  • As NAND technology evolves, waveform and protocol analysis can help to show how manufacturers have developed their approach over successive generations.

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